“Bit stuffing” is a well known technique used in synchronizing data signals by “mapping” such signals from one data rate to a different data rate. For example, as shown in FIG. 1, plesiochronous signals, such as DS-1, DS-2 or DS-3 signals respectively characterized by 1.544 Mb/s, 6.312 Mb/s or 44.736 Mb/s clock rates, are commonly mapped from a plesiochronous link 10 to a SONET/SDH link 12 having a different characteristic clock rate, such as the 1.728 Mb/s rate of the SONET VT1.5 signal. An electronic device known as a “mapper” 14 performs the mapping operation. After transmission over SONET/SDN link 12, the signal is desynchronized (demapped) by “demapper” 16 which reconverts the SONET/SDH signal to a plesiochronous signal for transmission over another plesiochronous link 18.
The bit stuffing technique involves insertion (“stuffing”) of positive or negative bits into the data stream during the mapping operation. If these bit “stuffs” are performed in a regular and efficient manner they impose unacceptable low frequency jitter on the mapped data stream. It is very difficult to remove such low frequency jitter when the data stream is desynchronized (demapped), particularly in older “legacy” systems utilizing 40 Hz jitter filters. Consequently, the prior art has evolved various bit stuffing techniques for minimizing low frequency jitter by translating jitter energy to higher frequencies at which it is more easily removed.
One prior art technique utilizes phase lock loops (PLLs) incorporating voltage controlled oscillators (VCOs) having frequency characteristics governed by the level of a FIFO buffer (sometimes called an “elastic store”) through which the data stream is processed. However, VCO-based PLL techniques involve comparatively expensive analog circuitry.
In another prior art technique known as “threshold modulation” the sawtooth-like characteristic of the FIFO buffer fill level is monitored and used to perform dithering of the bit stuffing operation. This requires monitoring of the FIFO buffer depth, and access to the FIFO buffer pointers. Moreover, the frequency of the aforementioned sawtooth characteristic affects the higher frequency band into which the jitter energy is translated, constraining circuit design if the sawtooth frequency is fixed. Stuff requests are produced on the basis of phase comparisons relative to a threshold level which is cyclically varied or modulated with a waveform having the same period as the stuffing “superframe.” The phase comparison is governed by the elastic store write and read address pointers.
U.S. patent application Ser. No. 09/641,980 filed 21 Aug. 2000 and assigned to the assignee of the present invention (the '980 application), discloses a jitter frequency shifting “delta-sigma” (Δ-Σ) modulated signal synchronization mapper which utilizes a deltasigma synchronizer (DSS) containing a Δ-Σ modulator that functions as a notional voltage controlled oscillator (VCO) to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, thereby simplifying attenuation of the jitter energy when the data stream is desynchronized (demapped). The '980 application's Δ-Σ modulator is integrally coupled within a frequency-locked loop (FLL)—a leading lowpass filter and the Δ-Σ modulator form a coupled loop control circuit.
The '980 application's DSS is constrained in that the Δ-Σ modulator is inside the loop of the PLL. This does not allow flexibility in selecting the frequency offset measurement frequency. This may present a problem in systems that employ a relatively slow bit-stuffing clock, as the waiting time jitter generated by the phase detector (frequency offset measurement block) could become significantly large.
This invention seeks to address or at least ameliorate the foregoing problems. Unlike the aforementioned threshold modulation technique, this invention (like that described in the '980 application) utilizes direct measurement of the frequency offset between a recovered line clock and a system clock, with no threshold modulation based on generation of bit stuff commands.